1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly, to a technique to test a non-volatile semiconductor memory device.
2. Description of the Related Art
FIG. 1 shows a conventional non-volatile semiconductor memory device. A conventional non-volatile semiconductor memory device MEM has a command decoder CMDEC, an internal voltage generator IVG, an address decoder ADDEC, a memory cell array MCA, a row decoder RDEC, a source selector SSEL, a column decoder CDEC, a Y gate YGT, a sense amplifier SA, a data latch DLAT, and a data input/output circuit DIO.
Based on external control signals supplied via a pulse input pin PLS, a reset pin RST, and a mode set pin MD, the command decoder CMDEC shifts to a desired operation mode (a read operation mode, a write operation mode, an erase operation mode, or the like) to generate internal control signals (including a read command, a write command, an erase command, and the like) for controlling the internal voltage generator IVG, the address decoder ADDEC, the sense amplifier SA, the data latch DLAT, and the data input/output circuit DIO.
In response to the internal control signal supplied from the command decoder CMDEC, the internal voltage generator IVG generates an internal voltage to be used in the row decoder RDEC and an internal voltage to be used in the source selector SSEL by using external voltages supplied via power supply pins VDD, VSS. The address decoder ADDEC generates internal control signals for controlling the row decoder RDEC, the source selector SSEL, and the column decoder CDEC, based on an address supplied via an address input pin ADD and the internal control signal supplied from the command decoder CMDEC.
The memory cell array MCA is composed of a plurality of non-volatile memory cells MC arranged in matrix. Each of the memory cells MC is constituted of a transistor having a control gate and a floating gate. The control gate of the memory cell MC is connected to a word line WL, a drain of the memory cell MC is connected to a bit line BL, and a source of the memory cell MC is connected to a source line SL.
The row decoder RDEC selects a desired word line WL in the memory cell array MCA based on the internal control signal supplied from the address decoder ADDEC and sets the selected word line WL to a predetermined voltage by using the internal voltage supplied from the internal voltage generator IVG. The source selector SSEL selects a desired source line SL in the memory cell array MCA based on the internal control signal supplied from the address decoder ADDEC and sets the selected source line SL to a predetermined voltage by using the internal voltage supplied from the internal voltage generator IVG.
The column decoder CDEC generates an internal control signal for controlling the Y gate YGT based on the internal control signal supplied from the address decoder ADDEC. The Y gate YGT selects a desired bit line BL in the memory cell array MCA based on the internal control signal supplied from the column decoder CDEC and connects the selected bit line BL to the sense amplifier SA or the data latch DLAT. The sense amplifier SA, the data latch DLAT, and the data input/output circuit DIO are generally-known circuits that operate in response to the internal control signals supplied from the command decoder CMDEC, for the purpose of data exchange and so on between the memory cell array MCA and an exterior, and the like.
In the non-volatile semiconductor memory device MEM as structured above, an erase operation is executed by applying an electric field for discharging electrons from the gate of the memory cell MC selected by the row decoder RDEC and the source selector SSEL. Whether or not the erase of the memory cell MC has been completed is determined by an erase verify operation. The erase verify operation is executed in such a manner that an electric current of the memory cell MC selected by the row decoder RDEC and the source selector SSEL passes through the bit line BL, and the sense amplifier SA determines the erase completion via the Y gate YGT. The determination result by the sense amplifier SA is supplied to an input/output pin IO via the data input/output circuit DIO.
When an erase voltage (voltage of the word line WL for the erase operation) is excessively applied to the memory cell MC, a threshold voltage of the memory cell MC becomes negative (the memory cell MC comes to be in an over-erased state). If there is a memory cell MC in the over-erased state, an electric current of the memory cell MC in the over-erased state passes through the bit line BL in the read operation and the like. As a result, the sense amplifier SA cannot discriminate an electric current of a memory cell MC in a programmed state from the electric current of the memory cell MC in the over-erased state both connected to the same bit line BL, which may cause erroneous data read. Therefore, it is necessary to avoid applying an excessive erase voltage to the memory cells MC.
FIG. 2 shows an erase test method for the non-volatile semiconductor memory device in FIG. 1. In an erase test flow shown in FIG. 2, Steps S501˜S508 are operations executed in an external testing apparatus.
At Step S501, a value of a variable N representing the number of erase times (the number of times an erase pulse is generated) is set to 0. Thereafter, the erase test shifts to Step S502.
At Step S502, an address supplied to the address input pin ADD is set to a start address of the memory cell array MCA. Thereafter, the erase test shifts to Step S503.
At Step S503, the erase verify is executed. If the erase verify results in pass determination, the erase test shifts to Step S504. If the erase verify results in fail determination, the erase test shifts to Step S506.
At Step S504, the address supplied to the address input pin ADD is incremented. Thereafter, the erase test shifts to Step S505.
At Step S505, it is determined whether or not the address supplied to the address input pin ADD matches a test termination address (an address after an end address of the memory cell array MCA is incremented). If the address supplied to the address input pin ADD matches the test termination address, the erase test is normally finished. If the address supplied to the address input pin ADD does not match the test termination address, the erase test shifts to Step S503.
At Step S506, the erase pulse to be supplied to the pulse input pin PLS is generated. Consequently, the erase operation of the non-volatile semiconductor memory device MEM is executed. Thereafter, the erase test shifts to Step S507.
At Step S507, 1 is added to the value of the variable N. Thereafter, the erase test shifts to Step S508.
At Step S508, it is determined whether or not the value of the variable N has exceeded a maximum number of erase times Nmax. If the value of the variable N has exceeded the maximum number of erase times Nmax, the erase test is anomalously finished. If the value of the variable N has not exceeded the maximum number of erase times Nmax, the erase test shifts to Step S503.
Further, Japanese Unexamined Patent Application Publication No. Hei 8-31189 and Japanese Unexamined Patent Application Publication No. 2004-241045 disclose, for example, a technique to simultaneously conduct erase tests on a plurality of non-volatile semiconductor memory device.
In erase tests of non-volatile semiconductor memory devices such as flash memories, generally, plural non-volatile semiconductor memory devices are subjected to the erase tests simultaneously in order to shorten the test time. In conducting the erase tests on a plurality of non-volatile semiconductor memory devices that are different in the number of erase times (the time taken to complete the erase of all the memory cells) by using simple external testing apparatuses having the same power source, an external control signal for causing the non-volatile semiconductor memory devices to execute the erase operation is supplied commonly to all of the plural non-volatile semiconductor memory devices. Because of this, the external control signal is continuously supplied to all of the non-volatile semiconductor memory devices as long as there remains any non-volatile semiconductor memory device with the erase of all the memory cells not completed. Consequently, erase operations are executed more than necessary even on the non-volatile semiconductor memory devices with the erase of all the memory cells completed.
The number of erase times required for completing the erase of all memory cells in a non-volatile semiconductor memory device (the number of times the erase operation is executed) is greatly influenced by manufacturing conditions and the like of the non-volatile semiconductor memory device. Therefore, in a case where the erase tests are conducted on a plurality of non-volatile semiconductor memory devices simultaneously according to the erase test flow shown in FIG. 2, when an anomalous termination condition (the maximum number of erase times Nmax) of the erase test flow is set for one which requires the largest number of erase times, unnecessary erase pulses are supplied to the other non-volatile semiconductor memory devices, resulting in the execution of erase operations more than necessary.
Further, Japanese Unexamined Patent Application Publication No. Hei 8-31189 discloses a method in which conditional branch processing is executed for each memory cell in each of the non-volatile semiconductor memory devices by hardware and software of the external testing apparatus. However, this complicates the configuration of the external testing apparatus. Japanese Unexamined Patent Application Publication No. 2004-241045 discloses another method in which the erase pulse is continuously supplied until the prescribed maximum number of erase times, which makes the test time fixed and makes the shortening thereof difficult accordingly.